1. Field of the Invention
The invention relates to a digital oscillator, especially for a desynchronizer within a transmission system.
2. Description of the Prior Art
In principle it is possible for a digital oscillator to be constructed of a number of n dividers with n different division ratios, which, on one hand, are connected with a quartz [crystal oscillator] for the generation of the basic frequency to be divided, and, on the other hand, connected to a multiplexer. The multiplexer is so triggered that, for a desired target frequency, there is switching to that divider which supplies it. This, in turn, can be taken off at the multiplexer. The triggering occurs, e.g., via a control into which the digital oscillator is incorporated.
Within a message transmission system the digital oscillator serves to generate a plesiochronous frequency, of, for example, 2.048 MHz, 34.368 MHz, or 44.736 MHz as target frequency. In addition, it is a part of a desynchronizer, which in urn forms the interface between the synchronous and the plesiochronous clock domains within the transmission system. Two signals are plesiochronous if their bit rates are indeed nominally equal, yet in fact are able to diverge within a given tolerance from the nominal value. The desynchronizer thus serves among other things for taking the plesiochronous 2 Mbit/s, 34 Mbit/s or 45 Mbit/s clock from a data signal.
A desynchronizer of a transmission system, e.g. one known from EP 0 404 268 A2, comprises a buffer memory, a writing address counter, a reading address counter, and a filter, connected on the output side to a digital oscillator, especially an NCO (numerically controlled oscillator). The clock is generated in a digital phase-locked loop (PLL) regulating circuit which comprises the filter and the NCO. On the input side, the filter is connected to the writing address counter and to the reading address counter. The filter issues a control signal for the NCO which is working in principle as a divider, and which creates the desired target frequency from a base or input frequency through division.
An essential requirement of such an NCO or digital oscillator is that the time [duration] of the "high" level of the generated clock, i.e. of the target frequency, be constant. In such a case this clock can be used to generate an HDB3 pulse as specified according to CCITT Recommendation G 703 for 34 Mbit/s or 45 Mbit/s, without the possibility that a quantization of the digital oscillator could have a negative influence on the pulse generation. According to this specification the duration of a positive or negative pulse of such an HDB3 signal clock must not exceed or fall below a specific tolerance.